1. Field of the Invention
The present invention relates generally to analog to digital converters, and more specifically to multichannel converters.
2. Description of the Related Art
Many electronic systems, for example communication, instrumentation, and medical equipment, embed multiple data channels in a single device such that many signals can be received, processed and transmitted in parallel and at the same time.
For example, some radio systems using a technology called multiple-input and multiple-output (MIMO), use multiple antennas at both the transmitter and receiver to improve communication performance. The signal processing between receiving antennas and transmitting antennas is performed in parallel on multiple signals.
In another example, an ultrasound system for medical applications collects signals from the human body from as many as 512 sensors, and then it processes and combines the information received by such sensors to enhance the image of tissues and organs.
A key block in such systems is an Analog-to-Digital Converter (ADC). The purpose of an ADC is to provide a digital version of an analog signal. In a typical multiple channel receiver, each analog signal is converted into digital format by an ADC.
For example, looking to FIG. 1, a four channel receiver has four ADCs 102n. This arrangement has several limitations. For example:
A mismatch between physically different ADCs 102 due to fabrication variations may affect the accuracy of post processing in a Digital Signal Processing “DSP”) block.
Balanced clock distribution 106 among different ADCs 102n can be difficult. Any clock skew may lead to random offsets between channels in the sampling instants of the different channels. In systems where synchronous sampling is required, clock path mismatch may limit performance.
The power consumption of an n-channel system is often at least n times the power consumption of a single ADC.
If a number n ADCs 102n are integrated in the same silicon, and the test yield of a single ADC is less than 100%, the yield of the system will be reduced to pn.
The front-end circuit of an ADC often comprises a block denominated a sample-and-hold (S&H) circuit. The function of an S&H is to sample an analog signal in discrete-time analog quantities. The remainder of the ADC quantizes such discrete time analog samples into discrete levels. A digital code, for example binary, thermometer, or the like, is then associated with each quantized level.
FIG. 2 is an example of a typical sample-and-hold function. The analog input 202 is connected to a capacitor 204 via a switch 208 which may be turned ON (closed) or OFF (open) in response to a sampling clock 206. When the switch 208 is ON, the analog input 202 will charge the capacitor 204 (or, said differently, the capacitor samples the input), but as soon as the switch 208 is turned OFF, the capacitor 204 is disconnected from the input, thereby holding the charge that was provided by the input 202. An ADC may at a later time be electrically connected to an output terminal 210 and convert the held charge to a digital value.
FIG. 3 illustrates an exemplary prior art alternative to multiple ADCs. As shown, a single ADC 302 is clocked by sample clock 305 and switches 304 between analog inputs 308 responsive to the sample clock 305. The resulting digital output is 1-2-3-4-1-2-3-4-1-2 . . . and is provided to DSP 304.
However, such systems are only usable for low bandwidth systems wherein clock skew and other issues are not significant at their low conversion rates. What is needed is an ADC system employing a single ADC while minimizing the above-listed problems.